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AVX-512: Add perfomtest-compliant headers to test cases

AVX-512: Add perfomtest-compliant headers to test cases test/avx512*.asm files are now tested by using perfomtest.pl Refer to pefomtest help message for the usage. Signed-off-by: Jin Kyu Song...

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parser: simplify code by keeping a pointer to the current operand

parser: simplify code by keeping a pointer to the current operand There is an awful lot of syntax-heavy "result->oprs[operand]" going on; simplify by making a pointer to the current operand....

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parse: factor out mref parsing

parse: factor out mref parsing Factor out the parsing of an mref from parse_line(). In order to support the [base,index] syntax we need to be able to parse an mref in two steps. Signed-off-by: H....

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parser: support split base,index effective address

parser: support split base,index effective address Mostly intended for the "mib" expressions in BNDLDX/BNDSTX. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Signed-off-by: Jin Kyu Song...

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disasm: add support for emitting split EA format

disasm: add support for emitting split EA format Add support for emitting split EA format in the disassembler, indicated by the MIB instruction flag. Signed-off-by: H. Peter Anvin...

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MPX: Add MPX instructions

MPX: Add MPX instructions Added MPX instructions and corresponding parser and encoder. ICC style mib - base + disp and index are separate - is supported. E.g. bndstx [ebx+3], bnd2, edx -> ebx+3 :...

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MPX: Add BND prefix for brach instructions

MPX: Add BND prefix for brach instructions BND prefix is used for adding bounds checking protection across flow control changes such as call, ret, jmp and jcc calls. Signed-off-by: Jin Kyu Song...

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MPX: Add test cases for MPX

MPX: Add test cases for MPX MPX test asm files are added. These include all three different styles of mib syntax (NASM, ICC and gas). Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> [DBH]...

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SHA: Add SHA instructions

SHA: Add SHA instructions New instruction extensions of SHA family are added. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> [DBH] insns.dat [DBH] insns.h

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SHA: SHA test cases

SHA: SHA test cases 32bit and 64bit test asm files. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> [DBH] test/sha-64.asm [DBH] test/sha.asm

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iflags: Use UINT64_C() for 64bit values

iflags: Use UINT64_C() for 64bit values UINT64_C() macro is used for iflags as it becomes 64bit. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> [DBH] insns.h

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REX: Set REX bits in accordance with 32-register environment

REX: Set REX bits in accordance with 32-register environment REX.RXB bits were set for high-8 registers previously. Since high-16 zmm registers are newly added, those bits should be set as one bit of...

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MPX: Adapt GAS's mib syntax with an index reg only

MPX: Adapt GAS's mib syntax with an index reg only GAS uses *1 multiplier for explicitly marking an index register in mib operand. e.g.) [rdx * 1 + 3] is equivalent to [3, rdx] in NASM's split EA...

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MPX: Move BND prefix indication from bytecode to iflags

MPX: Move BND prefix indication from bytecode to iflags As BND prefix validity check conflicts with jcc8 prefix, IF_BND is added for the instruction templates which can have bnd prefix for preserving...

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AVX512: Update instruction group

AVX512: Update instruction group CPUID bit for vptestnm[dq] changed. vptestnm[dq]: AVX512CD -> AVX512F Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> [DBH] insns.dat

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PREFETCHWT1: Add a new instruction flag

PREFETCHWT1: Add a new instruction flag PREFETCHWT1 instruction's CPUID was TBD before. Now it has its new CPUID bit : PREFETCHWT1 Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> [DBH]...

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AVX-512: Add {evex} instruction prefix

AVX-512: Add {evex} instruction prefix For instructions that can be encoded either in VEX or EVEX, {evex} forces nasm to encode in EVEX. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>...

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Build: Suppress warning messages

Build: Suppress warning messages Giving a correct printf format specifier supresses the warning message. And a local pointer variable is initialized with NULL. Signed-off-by: Jin Kyu Song...

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match: Improve broadcast opsize matching

match: Improve broadcast opsize matching Broadcasting operand size is different from the original operand size because 32b or 64b element is repeated to form a vector. So when matching a broadcasting...

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match: Check the number of elements in broadcasting operands

match: Check the number of elements in broadcasting operands The broadcasting decorator {1to##} must describe exactly how many times the memory element is repeated in order to clearly match the...

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